1. Field of the Invention
The present invention relates to a semiconductor memory device in which a pair of bit lines are precharged prior to data read access, and, in a data read mode, a potential difference between the pair of bit lines is amplified by a sense amplifier, in order to sense the data.
2. Description of the Related Art
In a conventional synchronous semiconductor memory device, a synchronous clock signal is used as an enable signal for a sense amplifier for sensing data.
FIG. 1 is a circuit diagram of a data read system circuit of a memory cell contained in a conventional synchronous semiconductor memory device.
Memory cell 14 includes a latch circuit 15, and n-channel MOS transistors 16 and 17 which serve as transfer gates and are inserted between the latch circuit 15 and a pair of bit lines 11 and 11, respectively. The gates of the transistors 16 and 17 are connected to the word line 12 which, along with precharge line 13, is intersected by bit lines 11 and 11.
A precharge circuit section 18 includes p-channel MOS transistors 19 and 20, one terminal of each of which is connected to the corresponding one of the pair of bit lines 11 and 11, the other terminal of each being connected to a power source voltage Vcc, and a p-channel MOS transistor 21 connected between the bit lines 11 and 11. Gates of the transistors 19, 20, and 21 are connected to the precharge line 13.
A potential difference between the bit lines 11 and 11 is input across the gates of n-channel MOS transistors 23 and 24, to which the bit lines are connected, respectively. P-channel MOS transistors 25 and 26 are inserted between the power source voltage Vcc and one terminal of the transistor 23 and between the power source voltage Vcc and one terminal of the transistor 24, respectively. The gates of transistors 25 and 26 are connected to each other, and are commonly connected to a connecting node SA located between the transistors 25 and 23. An n-channel MOS transistor 27 having a gate for receiving an enable signal for differential type sense amplifier 22 is inserted between the other terminal of each of the transistors 23 and 24, and a ground voltage Vss. A sensing result of the sense amplifier 22 is obtained at a connecting node SB located between the transistors 24 and 26, and is output as an output Out through two inverters 28 and 29.
Reference numeral 30 denotes a read control circuit including inverters 31, 32, and 34, and a NAND gate 33. A synchronous clock signal CK having a constant frequency is supplied to the inverters 31 and 32 located in separate signal paths, and is inverted by the inverters 31 and 32. The signal inverted by the inverter 31 is supplied as a precharge signal PR to the precharge line 13. The signal inverted by the inverter 32 is supplied to one input terminal of the 2-input NAND gate 33, the other input terminal of the gate 33 receiving a read/write signal RW. An output from the NAND gate 33 is supplied in the form of a read control signal RD via the inverter 34, to the gate of the transistor 27 contained in the sense amplifier 22.
FIG. 2 is a timing chart showing waveforms of sections within the circuit shown in FIG. 3, when in the read mode, the read/write signal RW being set at "H" level in this mode. A read operation performed by the circuit shown in FIG. 3 will now be described hereinafter, with reference to the above-mentioned timing chart.
When the signal CK goes to "H" level, the precharge signal PR goes to "L" level. As a result, the transistors 19, 20, and 21 in the precharge circuit 18 are turned on, and the bit lines 11 and 11 are precharged at "H" level.
When the clock signal CK goes to "L" level from "H" level, the precharge signal PR goes to "H" level, and the precharge operation in respect of the bit lines 11 and 11 is completed. When the signal CK goes to "L" level from "H" level, the signal RD goes to "H" level from "L" level, and the transistor 27 is turned on, as a result of which the sense amplifier 22 is enabled.
The word line 12 is selected by a decoder (not shown), and a signal WD goes from "L" level to "H" level, with the result that the transistors 16 and 17 in the memory cell 14 are turned on, and memory data "1" or "0" in the latch circuit 15 is read out on the bit lines 11 and 11. Bit line potentials BT and BT are set in accordance with the readout data. If the potential BT is set at "H" level and the potential BT is set at "L" level, the potential BT is reduced with time. When a predetermined period of time has elapsed and the difference between the potentials BT and BT is set to be .DELTA.V or more, the logic level of the node SB in the sense amplifier 22 becomes "H", and this "H"-level signal is output as the output Out through the inverters 28 and 29.
If the potential BT is set at "L" level and the potential BT is set at "H" level, the potential BT is reduced with time. As a result, the logic level of the node SB becomes "L"; hence the output Out serves as an "L"-level signal.
When the clock signal CK again goes to "H" level, a precharge operation in respect of the bit lines 11 and 11 is started by the precharge circuit 18. On the other hand, the signal RD goes to "L" level, and the sense amplifier 22 is disabled.
The above-mentioned conventional memory device has a problem, however, in that current consumption in the read mode is high, due to a feedthrough current being flown over an extended period of time.
More specifically, the operation period of the sense amplifier 22 depends on the level of the signal RD, and for this reason, the sense amplifier 22 is kept enabled during a period t wherein the signal RD is set at "H" level. In other words, the sense amplifier 22 is not disabled until the clock signal CK goes to "H" level after the logic level of the node SB is determined. Assume that the potential BT is set at "H" level and the potential BT is set at "L" level, in accordance with memory data of the memory cell 14. In this case, the transistor 23 is turned on, and the potential of the node SA is reduced. Thereafter, when the potential of the node SA exceeds an absolute value of the threshold voltage of the transistor 25, the transistor 25 is turned on. As a result, a feedthrough current is generated which passes through the transistors 25, 23, and 27, and flows during the time t after the logic level of the node SB is determined. As a result, current consumption in the read mode is high.
Thus, as described above, the conventional device has a problem in that its current consumption is high, due to the length of time the feedthrough current is supplied to the sense amplifier.